RESUME

Computer Science Graduate Research Assistant

​2019 - present

 

• Parallelized Genome Assembly; Parallelized a Particle Simulation; Optimized Matrix Multiplication

• Parallelized the optical flow algorithm using Cuda, OpenMP, and MPI programming models

• Mentored over 200 undergraduate scholars for Computer Organization Course. I taught students how to design, simulate, and implement a 32-bit Pipelined MIPS processor.

• Published the paper: “ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation” in ASAP conference

• A survey in progress: “FPGA implementation for vision algorithms.”

• A paper in progress: “Parallel and pipeline Lucas Kanade Optical Flow."

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Digital Electronics Research and Teacher Assistant

​2013 - 2018

 

• Published the journal paper: “Accurate prediction with statistically-based models for CNT-FET application.” Different statistical-based convex algorithms, including Random forest, boosting, and support vector regression (SVR), as alternatives to conventional artificial neural networks (ANN), are evaluated and optimized for carbon nanotube (CNT) field-effect transistor (FET) modeling.

• Published the paper: “Statistical feature reduction for human activity recognition (HAR) task.” Using P-values for correlation analysis, and evaluating the significance of features with the most substantial mean decreasing accuracy, a statistical-based feature reduction is proposed. Pattern recognition models that used this statistical feature reduction, instead of principal component analysis (PCA), showed less complexity that was suitable for hardware implementation.

• Published the conference paper: “ASIP design for two-dimensional CORDIC based DFT and DCT algorithms.” In this research, I have proposed a CORDIC-based application-specific instruction-set processor(ASIP) for two-dimensional discrete Fourier transform (DFT) and discrete cosine transform(DCT). Satisfying the critical points in power consumption, total delay, manufacturing cost, and productivity, I designed an ASIP architecture to replace the current Application-Specific integrated circuits(ASICs) and general-purpose processors (GPPs).

• Machine Learning:  Teacher Assistant at Shahid Beheshti University for Graduate students. In this course, I covered machine learning techniques such as Supervised Learning, Multivariate Methods, Multilayer Perceptrons, Kernel Machines, Nonparametric Methods, and Clustering.

• FPGA design and implementation of high throughput large-scale complex matrix inversions for multiple inputs, multiple outputs (MIMO) wireless applications. Gauss-Jordan algorithm is implemented as an efficient technique, and it is optimized for high-throughput matrix inversion in MIMO wireless applications.

• I worked on reliability analysis and FPGA implementation of fault-tolerant systems. This project used hardware description language along with SystemC as a software designing counterpart for implementing both information and modular redundancy. The theoretical reliability analysis of these models is also evaluated using MATLAB simulation environment.

• I proposed a block-level ASIC design for sigmoid function for deep learning applications. This project proposes an accurate and area-efficient analog activation function for feed-forward artificial neural networks (ANNs) using TSMC 90 nm technology.

• Targetting the Spartan-6 FPGA family, I have designed, simulated, and implemented the AES cryptography algorithm. I proposed an optimized RTL design based on hardware description language; simulation happened on ActiveHDL and implementation on the ISE design suite, respectively.

• I designed a Low power and high-frequency AISC layout for an 8-bit multiplier using pseudo-nMOS and pseudo-pMOS gates.

 

Electronics and Electrical Engineering 

​2008 - 2013

 

• Design and implementation of the GSM transmitter module using AVR microcontroller Programming AVR chips by using C interface and evaluating the module in the Proteus simulation environment.